This invention relates to photovoltaic devices, particularly photovoltaic devices comprising thin layers of semiconductor materials, such as thin layers of monocrystalline or multicrystalline silicon. More particularly, this invention relates to photovoltaic devices comprising monocrystalline or multicrystalline silicon semiconductor materials. These devices which comprise doped wafers of monocrystalline or multicrystalline silicon convert light energy into electrical energy.
These photovoltaic devices, also known as photovoltaic cells, are used to convert light energy into electrical energy. Photovoltaic cells can be used to generate energy (solar cells) or they can be used as photodector elements in other devices. Photovoltaic cells are a source of renewable energy. However their use is limited by their electrical output. Typically, many photovoltaic cells are arranged in one or more panels or modules in order to generate sufficient power required for a desired commercial or consumer application. Photovoltaic cells having greater efficiency result in modules with greater electrical power output. Therefore, it is necessary to be able produce a large number of highly efficient photovoltaic cells. It would be very desirable to be able to reduce the manufacturing cost, increase the efficiency of light conversion, or both, of such photovoltaic devices. The photovoltaic cells of this invention are highly efficient in comparison to conventionally produced cells and the process of this invention allows these highly efficient cells to be produced more easily than conventionally produced photovoltaic cells.
Most photovoltaic cells are fabricated from either monocrystalline silicon or multicrystalline silicon. Silicon is generally used because it is readily available at a reasonable cost due to its use in the microelectronics industry and because it has the proper balance of electrical, physical and chemical properties for use to fabricate photovoltaic cells. During the manufacture of photovoltaic cells, silicon is doped with a dopant of either positive or negative conductivity type, and is typically cut into thin substrates, usually in the form of wafers or ribbons, by various methods known in the art. Throughout this application, the surface of the substrate, such as a wafer, intended to face incident light is designated as the front surface and the surface opposite the front surface is referred to as the back surface. By convention, positive conductivity type is commonly designated as “p” and negative conductivity type is designated as “n.” In this application, “p” and “n” are used only to indicate opposing conductivity types. In this application, “p” and “n” mean positive and negative respectively but can also mean negative and positive respectively. The key to the operation of a photovoltaic cell is the creation of a p-n junction, usually formed by further doping the front surface of the silicon substrate to form a layer of opposite conductivity type from the doped silicon substrate. Such a layer is commonly referred to as the emitter layer. In the case of a p-doped substrate, the emitter layer would be formed by doping the front surface with an n-type dopant. The p-n junction is the interface between the p-doped region and the n-doped region. The p-n junction allows the migration of electron-hole pairs in response to incident photons which causes a potential difference across the front and back surfaces of a substrate wafer.
Fabrication of a photovoltaic cell generally begins with a p-doped substrate. The substrate, typically in the form of a wafer, is then exposed to an n-dopant to form an emitter layer and a p-n junction. Typically, the n-doped layer is formed by first depositing an n-dopant onto the surface of the substrate using techniques commonly employed in the art, such as spray on, spin on, chemical vapor deposition, or other deposition methods. After deposition of the n-dopant upon the substrate surface, the n-dopant is driven into the surface of the silicon substrate to further diffuse the n-dopant into the substrate surface. This “drive-in” step is commonly accomplished by exposing the wafer to heat, often in combination with a gas stream comprising oxygen, nitrogen, steam, or a combination thereof. The n-doped layer is commonly referred to as an emitter layer.
A p-n junction is formed at the boundary region between the n-doped layer and the p-doped silicon substrate. The p-n junction is required to allow the charge carriers to migrate in response to incident light. Ideally, the emitter layer would be limited to the surface of the wafer designed to be oriented towards incident light, which is referred to as the front surface, and, consequently, the p-n junction would be proximal to the front surface only. In practice, however, doping will also occur on the edges and the opposing surface of the wafer (the back surface). This results in an emitter layer which covers the entire surface of the wafer and a p-n junction proximal to the entire surface of the wafer from which an electric current cannot be drawn. It is therefore necessary to electrically isolate the front and back junctions. The wafer can be masked so that an emitter layer forms only on selected surfaces of the wafer. However, such masking requires additional time, materials, and handling, particularly if it must be removed later. It would be advantageous if such a masking step could be eliminated or combined with another process step.
U.S. Pat. No. 5,082,791 to Micheels et al. discloses the use of an excimer laser to isolate the front p-n junction. Micheels et al. use an excimer laser to form a trench on the back surface of the substrate. The trench is deeper than the n-doped layer and extends along the entire periphery of the back surface at a fixed distance from the edges of the back surface.
U.S. Pat. No. 4,158,591 to Avery et al., which is incorporated by reference herein, discloses a method to electrically isolate the front p-n junction by removing the p-n junction from the edges of the substrate without removing the front and rear p-n junctions. Isolation of the front p-n junction by removing the edge p-n junction is commonly referred to as “edge junction isolation.” The edge junction isolation method disclosed by Avery et al. has come to be known as “coin stacking.” In the coin stacking process, the photovoltaic cells are stacked face to face and the edges are removed. The edges can be removed by plasma etching, by wet chemical etching, by physical grinding or other known methods. U.S. Pat. No. 5,871,591 to Ruby et al., incorporated by reference herein, describes a process commonly used to fabricate photovoltaic cells. The process described by Ruby et al. includes an edge junction isolation step accomplished by the coin stacking process.
Use of the coin stacking method results in lower cost and higher production rate when compared to previous methods for isolating the front p-n junction but also has several disadvantages. The physical stacking of the wafers can cause some wafers to be damaged. It is advantageous to minimize the thickness of the silicon substrate because the silicon substrate is a significant portion of the cost and size of a photovoltaic cell. Unfortunately, the coin stacking method significantly limits the thinness of the wafers. The fraction of wafers that are damaged during coin stacking increases as the wafer thickness decreases. As a result, coin stacking limits the cost savings achievable through use of thinner wafers. Another disadvantage of the coin stacking method is that it decreases the area of the front surface of a photovoltaic cell. Ideally, removal of the edge junction would result only in the removal of the n-doped region. In practice, however, some additional depth is also removed from the edge. Typically, the useful surface area of the front surface is decreased by about 2 percent, resulting in a corresponding 2 percent decrease in the energy output of the photovoltaic cell.
Efficiency of a photovoltaic cell is determined by the capacity of the cell to convert incident light energy into electrical energy. Several modifications to the design and production of photovoltaic cells have been developed to increase conversion efficiency. Chapter 4 of Crystalline Silicon Solar Cells, by Martin A. Green, Photovoltaics Special Research Centre, University of New South Wales, which is incorporated by reference herein, discusses photovoltaic cell developments that increase cell efficiency including the use of texturing, antireflective coatings, surface passivation, and back surface fields.
Texturing of a photovoltaic cell reduces reflection of incident light by the photovoltaic cell surface. By reducing reflection, more incident light is available for conversion by the photovoltaic cell. Texturing is typically accomplished by chemical etching and in particular by anisotropic etching of the silicon substrate. Antireflective coatings further reduce the reflection of incident light at the photovoltaic cell surface. Antireflective coatings are typically applied by forming an oxide or silicon nitride layer on the wafer.
Surface passivation increases efficiency of a photovoltaic cell by decreasing electronic activity at the surface of the photovoltaic cell. Several methods of surface passivation are known in the art, including the use of oxide or silicon nitride coatings.
Back surface fields increase the efficiency of photovoltaic cells. Back surface fields are particularly desirable for photovoltaic cells with thin substrates. Photovoltaic cells with thin substrates have many benefits, including reduced material requirements, lower cost and less weight, but also exhibit a decrease in efficiency, generally attributed to an increase in the diffusion of minority charge carriers to the back surface of the cell. Back surface fields decrease such diffusion of minority carriers and increase the current generated by majority carriers. U.S. Pat. No. 5,899,704 to Schlosser et al., incorporated by reference herein, discloses a method of creating a back surface field. Generally, a back surface field is created by incorporating a thin layer at the back surface which is heavily doped with a dopant of opposite conductivity type from the emitter layer.
There is a need for a photovoltaic cell with high efficiency and preferably one that can be fabricated at low cost. More particularly, there is a need for a photovoltaic cell manufacturing process that isolates the front p-n junction of a silicon or other semiconductor substrate without the increased cell damage of the coin stacking method. There is also a need for a photovoltaic cell manufacturing process that allows for the use of less silicon through thinner wafers. The process of this invention provides such a photovoltaic cell and process.